The snoop based scheme is common used in both UMA and NUMA architectures, due to its flexibility and ease of scalability. In this post, we will discuss the state transition for snoop based scheme in both UMA and NUMA architectures. The protocol we are using is MSI protocol, i.e., a cache block can be in modified, shared or invalid state. Continue reading → Can you show the state transition for snoop-based scheme using MSI protocol?
We have discussed CPU pipelining and out-of-order scheduling in previous posts, and these are for increasing instruction-level parallelism. The next level of parallelism will be thread-level parallelism, or TLP. One solution to TLP is multiprocessors, i.e., a computer system consisting of multiple processors, typically controlled by one operating system and sharing the same memory address space.
Generally speaking, there are two multiprocessor architectures