What is the benefit of using half-cycle-path?

Until now, we focus on the timing of one-cycle-path or full-cycle-path. Sometimes, there may exist half-cycle-path in design. One example will be the launch flop is negedge triggered, while the capture flop is still posedge triggered.

We discussed the clock skew and how it affects STA in previous post. Equivalently, half-cycle-path can be modeled as one-cycle-path with clock skew δ = +T/2. It is obvious that hold time closure is easier while setup time closure is harder for half-cycle-path.

You may wonder what is the benefit of using half-cycle-path in the design.

Continue reading → What is the benefit of using half-cycle-path?

How to set mutually exclusive synchronous clock design constraints?

If there exists mutually exclusive synchronous clocks in the design, designers have several ways to specify the exclusivity of the clocks:

set_case_analysis
set_false_path
set_clock_groups -logically_exclusive
set_clock_groups -physically_exclusive

“set_case_analysis” is the most straightforward way, and it constrains which clock will propagate through. However, it leads to different timing modes, and increases tool total runtime.

For false paths or “exclusive” clock paths, DC will not optimize timing for them, and STA will not check timing for them either.

“set_false_path” is usually not preferred, since it can introduce undesired timing exceptions. False path still impacts the SI analysis.

“set_clock_groups” is the most recommended one, but there are some differences between “-logically_exclusive” and “-physically_exclusive”. “-physically exclusive” does not consider SI effect, while “-logically_exclusive” does.

Continue reading → How to set mutually exclusive synchronous clock design constraints?

How to set generated clock design constraints in Post-CTS run?

We discussed how to set multi-synchronous-clock design constraints, and we will look at how to define clock propagated through sequential logic or macros.

For clocks propagated through sequential logic or macros such as PLL, we need to define generated clocks. The first step, is to define the master clock or the source clock of the generated clock:

Continue reading → How to set generated clock design constraints in Post-CTS run?

How to set generated clock design constraints in Pre-CTS run?

We discussed how to set multi-synchronous-clock design constraints, and we will look at how to define clock propagated through sequential logic or macros.

For clocks propagated through sequential logic or macros such as PLL, we need to define generated clocks. The first step, is to define the master clock or the source clock of the generated clock:

Continue reading → How to set generated clock design constraints in Pre-CTS run?

How to set multi-synchronous clock design constraints?

We have covered single-clock design constraints for Pre-CTS run and Post-CTS run. In this post, we will look at a more interesting scenario: constraining multi-synchronous-clock design.

How to Constrain Multiple Clock Input Delay?

Let’s assume, the design uses clock “CLKC” with period of 2ns, and the register driving the inputs of the design uses clock “CLKB” with period 3ns. Both “CLKC” and “CLKB” are divided from the same reference clock.

Thus we can define “CLKC” as master clock and “CLKB” as virtual clock to the design, and set input delay accordingly.

Continue reading → How to set multi-synchronous clock design constraints?

How to set asynchronous clock design constraints?

Synthesis and STA tools will try to close timing between synchronous clocks, thus the tools need to know what clocks or paths are asynchronous, thus no timing closure is needed.

There are 2 ways to specify asynchronous design constraints. The first one is to use exceptions, i.e., specify “false path”. Even though intuitive and convenient, this approach is not recommended. If the path is not defined correctly and precisely, it may lead to unwanted “false path” where timing closure is required.

The more preferred approach is to use “set_clock_groups -asynchronous” command. In addition, this command still considers SI or noise analysis with infinite timing window. Thus this command is a more closer modeling to real silicon.

What are design / library objects? How to manipulate these objects?

Starting from this post, we will talk about commonly asked interview questions related to timing constraints or SDC. The most basic question is, what are design / library objects and how to manipulate these objects.

What Are Design / Library Objects?

These objects include:

    1. Design: defined by top level module
    2. Port: input, output and inout ports in the top level design
    3. Clock
    4. Cell: submodule instances in the design
    5. Pin: submodule instance ports
    6. Net: wire or registers to connect pins
    7. Library name
    8. Library cell

Continue reading → What are design / library objects? How to manipulate these objects?