What is the benefit of using half-cycle-path?

Until now, we focus on the timing of one-cycle-path or full-cycle-path. Sometimes, there may exist half-cycle-path in design. One example will be the launch flop is negedge triggered, while the capture flop is still posedge triggered.

We discussed the clock skew and how it affects STA in previous post. Equivalently, half-cycle-path can be modeled as one-cycle-path with clock skew δ = +T/2. It is obvious that hold time closure is easier while setup time closure is harder for half-cycle-path.

You may wonder what is the benefit of using half-cycle-path in the design.

Continue reading → What is the benefit of using half-cycle-path?

What is the procedure for timing ECOs? What are the timing fix techniques?

After PnR netlist is ready, STA engineers needs to do timing verification and perform timing ECO as needed. In this post, we will cover the timing ECO procedure, and some common timing fix techniques. A typical timing ECO procedure is shown in the diagram below:

Timing ECO Procedure

Continue reading → What is the procedure for timing ECOs? What are the timing fix techniques?