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How to set mutually exclusive synchronous clock design constraints?

If there exists mutually exclusive synchronous clocks in the design, designers have several ways to specify the exclusivity of the clocks:

set_case_analysis
set_false_path
set_clock_groups -logically_exclusive
set_clock_groups -physically_exclusive

“set_case_analysis” is the most straightforward way, and it constrains which clock will propagate through. However, it leads to different timing modes, and increases tool total runtime.

For false paths or “exclusive” clock paths, DC will not optimize timing for them, and STA will not check timing for them either.

“set_false_path” is usually not preferred, since it can introduce undesired timing exceptions. False path still impacts the SI analysis.

“set_clock_groups” is the most recommended one, but there are some differences between “-logically_exclusive” and “-physically_exclusive”. “-physically exclusive” does not consider SI effect, while “-logically_exclusive” does.

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How to set asynchronous clock design constraints?

Synthesis and STA tools will try to close timing between synchronous clocks, thus the tools need to know what clocks or paths are asynchronous, thus no timing closure is needed.

There are 2 ways to specify asynchronous design constraints. The first one is to use exceptions, i.e., specify “false path”. Even though intuitive and convenient, this approach is not recommended. If the path is not defined correctly and precisely, it may lead to unwanted “false path” where timing closure is required.

The more preferred approach is to use “set_clock_groups -asynchronous” command. In addition, this command still considers SI or noise analysis with infinite timing window. Thus this command is a more closer modeling to real silicon.