What are the differences between sync and async reset?

Synchronous reset has the following characteristics:

  1. It will not work if clock path has failures
  2. It tends to immune to glitches, since sync reset requires clock toggling
  3. It makes STA simpler and the whole design synchronous, since sync reset has no difference from regular data path
  4. Sync reset implementation will add a MUX at the input of each flop

Continue reading → What are the differences between sync and async reset?

What are common CDC considerations to transfer a pulse and to transfer multi-bit signals?

CDC considerations to transfer a pulse

Transfer a pulse from slow to fast clock domain, and from fast to slow clock domain, require separate handling.

Generally speaking, passing a signal from slow clock to fast clock is not a problem, since the loss of a pulse is less likely to happen. Based on Nyquist Theorem, if receiving clock frequency is at least 2x of sending clock frequency, then there will be no sampling loss.

Continue reading → What are common CDC considerations to transfer a pulse and to transfer multi-bit signals?

What is MTBF? Why can synchronizers handle CDC?

What is MTBF?

For most applications, it is important to calculate the Mean Time Before Failure / MTBF for any signal crossing a CDC boundary. In the context of MTBF, the failure means the output of the synchronizer still goes metastable. Obviously, a larger MTBF is favored over a smaller one, and the synchronization scheme needs to guarantee sufficient larger MTBF.

MTBF is inversely proportional to input data changing rate as well as receiving clock frequency. The faster of input data rate and receiving clock, the lower of MTBF.

Interviewees often mix the concept of input data changing rate with sending clock frequency, and incorrectly think sending clock frequency does impact MTBF. Faster sending clock does not necessarily imply faster input data changing rate.

It is required to flop the data in sending clock domain before synchronized in receiving clock domain. The output of combo logic often have glitches, i.e., it requires some time to settle. Without data flopping, the input data changing rate is effectively increased in receiving clock domain, decreasing the MTBF of CDC circuit.

Why can synchronizers handle CDC?

The simplest synchronization scheme is back-to-back flop synchronizer. Even though the output of the first stage is metastable, the CDC signal still have one more cycle to settle to a stable logic value. Therefore, synchronizers essentially increase the MTBF.

Conclusion

We recommend interviewees to further read Clifford E. Cummings’ paper “Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog”.

How to synchronize a signal/data from slow clock domain to fast clock domain?

Synchronization is an elementary aspect of designing. Interviewers usually assume that you have designed modules through multiple clock domains. Unfortunately, lots of new grads don’t have any experience on this or even never heard about it. It’s common that professors in colleges ignore this section. Continue reading → How to synchronize a signal/data from slow clock domain to fast clock domain?