Verilog uses “x” to model the unknown state, but it also introduces potential issues.
The simulation semantics of conditional constructs in Verilog, are not accurate enough to model the ambiguity inherent in un-initialized registers and power on reset values. When the unknown states that are modeled as ‘X’ values become control expressions, these issues are particularly problematic.
In this post, we will cover several techniques to detect and resolve x-related issues in RTL, including:
SystemVerilog Assertions / SVA
Gate Level Simulation
X-propagation in RTL Simulation
Continue reading → How to detect and resolve x-related issues in RTL?