Design a circuit that detects if one input is a delayed version of the other

Assuming 1b input A is generated by a random sequence, 1b input B is a delayed version of A. The delay value varies, and can be [1, 10] (inclusive).

Design a circuit, that takes A and B as inputs, and Y as output. If B is guaranteed to have 1s, then Y should be 1.

Continue reading → Design a circuit that detects if one input is a delayed version of the other

What is functional coverage? How to write functional coverage?

100% code coverage does not imply the completeness of verification. A fundamental limitation of code coverage is, it does not consider design specs and event sequences. Functional coverage is used address this limitation.

There are 2 ways to measure functional coverage. The first one is called covergroups, which is usually defined by DV engineers in test bench. See this post for more details.

The second one is called cover property, which is defined by designers. Usually cover properties can be specified inline with RTL, or in a separate file bind to RTL. Unlike assert property, cover property can be used to determine whether or not certain aspects of the designs functionality have been exercised. See this post for how to write cover properties.

How to detect and resolve x-related issues in RTL?

Verilog uses “x” to model the unknown state, but it also introduces potential issues.

The simulation semantics of conditional constructs in Verilog, are not accurate enough to model the ambiguity inherent in un-initialized registers and power on reset values. When the unknown states that are modeled as ‘X’ values become control expressions, these issues are particularly problematic.

In this post, we will cover several techniques to detect and resolve x-related issues in RTL, including:

Jasper Reset
SystemVerilog Assertions / SVA
Gate Level Simulation
X-propagation in RTL Simulation

Continue reading → How to detect and resolve x-related issues in RTL?

How to write SVA?

SVA is an important formal verification tool, that should be mastered by both designer and verification engineers.

Doulos has a page, perfectly illustrate how to write SVAs. We recommend interviewees to fully digest the content in that page.

In addition, SystemVerilog provides various of built-in methods, to aid and simplify SVA writing. We recommend interviewees to refer to this page.