Design a circuit that detects if one input is a delayed version of the other

Assuming 1b input A is generated by a random sequence, 1b input B is a delayed version of A. The delay value varies, and can be [1, 10] (inclusive).

Design a circuit, that takes A and B as inputs, and Y as output. If B is guaranteed to have 1s, then Y should be 1.

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Design A Programmable Sequence Detector

If the sequence is not predefined, then we can no longer use traditional FSM based sequence detector. Assuming we know the sequence to detect is 5-bit, then we can use the following circuit to detect the sequence.

The circuit consists of a 5-stage shift register, and a 5-bit configuration register. The sequence to detect is programmed in the configuration register, and the input sequence is compared with the configuration register every cycle.

Determine Whether An Infinite Sequence Is A Multiple of 5

Assuming incoming bit stream is one bit per cycle, design a circuit that detects whether the integer number formed by the bit stream is a multiple of 5.

The idea is to have an FSM consisting of 5 states, S0, S1, S2, S3, S4. Each state represents divided by 5 remainder in previous cycle. If FSM stays at S0, then it means the number could be divided by 5 in previous cycle; otherwise, the number was not a multiple of 5.

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