Typically, raw reset signals are synchronized before feeding into the logic. Thus reset is asserted asynchronously, and de-asserted synchronously.
In modern SoC design, it is not uncommon to have multiple reset domains. One reset domain may be under reset while the other is active. This can create problems if active domain is the consumer and domain under reset is the driver. When driver domain is under reset, there will be an asynchronous timing arc to the active domain, causing metastability issues to consumer domain.