A review of clock gating cells

In today’s SoC design, designers use clock gating cells everywhere to save dynamic power by reducing unnecessary clock activities inside the gated module. In addition, the use of ICGs can save area. Imagine a 512b data bus can be enabled or disabled using a single ICG, instead of using 512 muxes.

There are mainly 4 types of clock gating cells available:

Negative-Latch-AND-Gate Based ICG
OR-Gate Based ICG
Positive-Latch-OR-Gate Based ICG
AND-Gate Based ICG

Continue reading → A review of clock gating cells

How many types of isolation cells are there?

In previous post, we discussed why isolation cells are required in low power design. Let’s look at the types of isolation cells available in low power design.

  1. Isolation cell with clamp_value 1: In isolation mode, this cell drives 1 to its downstream logic. In normal mode, it acts as a buffer. This is similar to OR gate.
  2. Isolation cell with clamp_value 0: In isolation mode, this cell drives 0 to its downstream logic. In normal mode, it acts as a buffer. This is similar to AND gate.
  3. Latch type Isolation cell: In isolation mode, this cell will keep the latched value and drive its downstream logic. In normal mode it acts as a buffer. This is similar to Latch.
  4. Enable Level Shifter cell: This type of Isolation cells can perform both level-shifting and isolation functions. It is used where a signal crosses from one power domain to another, where the two voltage levels are different and the first domain can be powered down.

Why is isolation cell required in power aware design?

Two power domains interact if one contains the driver and the other contains the load. If the driving logic is powered down, the input to the receiving logic may float between 1 or 0. This can cause significant current to flow through the receiving logic, and the circuit may be damaged. In addition, an undriven input can also cause functional problems since it may float to an undefined value.

To avoid this problem, isolation cells shall be inserted between power domains to ensure that, input to receiving logic stays at a deterministic value. Isolation may be inserted for an input or for an output of the power domain. An isolation cell operates in two modes: normal mode, in which it acts like a buffer, and isolation mode, in which it clamps its output to a defined value. An isolation enable signal determines the operational mode of an isolation cell at any given time.

To avoid async timing arc from one power domain to the other, the transition between normal mode and isolation mode needs to be synchronous. Usually, in chip level, a power management module will activate / de-active isolation cells synchronously.

In next post, we will discuss the types of isolation cells used in power aware design.

How to reduce static power, dynamic power, and short-circuit dissipation power?

Static Power

Static power is proportional to circuit leakage current and supply voltage Vdd. Thus we have following ways to reduce static power:

  1. Dynamic Vth scaling by adjusting substrate bias
  2. Use multi-Vth devices in design
  3. Use high-Vth device whenever possible
  4. Dynamic supply voltage scaling
  5. Use multi-Vdd in design
  6. Shut off the power in standby mode

Continue reading → How to reduce static power, dynamic power, and short-circuit dissipation power?

What are static power, dynamic power and short-circuit dissipation power?

Static power is the circuit leakage power. Static power exists even if there is no activities. When power is applied to the transistors, transistors would leak current naturally due to physical characteristics of the silicon and manufacturing defects. Examples of static power include transistor drain to source leakage and silicon substrate leakage.

Dynamic power is the power used to charge or discharge transistor intrinsic capacitor. Dynamic power only exists when signals toggle either from low-to-high or high-to-low. For example, clock toggles every cycle, thus clock paths consumes huge amount of dynamic power if there is no clock gating.

Short-circuit dissipation power occurs when both NMOS and PMOS transistors are active for a small period of time, during which current will find a path directly from power rail to ground. Hence, this creates a short-circuit current. In first-order analysis, we assume 0 transistor rise / fall time during transition, and short-circuit dissipation power can be ignored. However, we shall assume finite transistor transition time in more accurate analysis, thus short-circuit dissipation power exists every time signal toggles.