If there exists mutually exclusive synchronous clocks in the design, designers have several ways to specify the exclusivity of the clocks:
“set_case_analysis” is the most straightforward way, and it constrains which clock will propagate through. However, it leads to different timing modes, and increases tool total runtime.
For false paths or “exclusive” clock paths, DC will not optimize timing for them, and STA will not check timing for them either.
“set_false_path” is usually not preferred, since it can introduce undesired timing exceptions. False path still impacts the SI analysis.
“set_clock_groups” is the most recommended one, but there are some differences between “-logically_exclusive” and “-physically_exclusive”. “-physically exclusive” does not consider SI effect, while “-logically_exclusive” does.