Hazards and solutions: a case study using MIPS 5-stage pipeline

The CPU pipelining introduces throughput increasing and possible higher clock frequency, but it does not come for free. By allowing multiple instructions being executed in parallel, CPU designers need to take care of the following hazards:

Structural hazards
Data hazards
Control hazards

In this post, we will discuss these hazards in detail and use MIPS 5-stage pipeline for case study.

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What does MIPS 5-stage pipeline looks like?

MIPS 5-stage pipeline is a classic way to illustrate CPU pipelining, and it is a common interview questions for new grads and junior engineers. The 5-stage pipeline consists of the following stages:

IF – instruction fetch
ID – instruction decode and operand fetch
EX – instruction execution
MEM – memory access
WB – write back

Continue reading → What does MIPS 5-stage pipeline looks like?