What is Conformal LEC flow? How does Conformal LEC perform key point mapping?

We already discussed why designers need to do LEC, and we will talk about Conformal LEC flow in this post.

In LEC setup, there are several steps that designers need to follow:

    • Read and elaborate reference design
    • Read and elaborate revised design
    • Specify “notranslate modules” for blackboxing if the module is a macro, or the module has been LECed in block level
    • Set certain constraints, for example, when comparing between RTL and synthesis netlist, set case analysis to ignore scan ports

Continue reading → What is Conformal LEC flow? How does Conformal LEC perform key point mapping?

What is LEC? Why should we do LEC?

Logical Equivalence Check, or LEC, is a formal verification method, to compare revised design with reference design. There are several circumstances where LEC is required, for example:

  1. Designers need to compare synthesis netlist (revised design) with RTL (reference design), to make sure synthesis optimization and scan insertion do not alter designers’ intent
  2. Physical designers need to compare PnR netlist (revised design) with synthesis netlist (reference design), to make sure the PnR results and timing ECOs do not change synthesis netlist functionalities
  3. Designers may perform ECOs for new feature addition and bug fix. There should not be any mismatch between ECOed RTL and synthesis netlist

The most common LEC tools include Cadence Conformal LEC, and Synopsys Formality. We will focus on Cadence Conformal LEC flow from next post.