What is the benefit of using half-cycle-path?

Until now, we focus on the timing of one-cycle-path or full-cycle-path. Sometimes, there may exist half-cycle-path in design. One example will be the launch flop is negedge triggered, while the capture flop is still posedge triggered.

We discussed the clock skew and how it affects STA in previous post. Equivalently, half-cycle-path can be modeled as one-cycle-path with clock skew δ = +T/2. It is obvious that hold time closure is easier while setup time closure is harder for half-cycle-path.

You may wonder what is the benefit of using half-cycle-path in the design.

Continue reading → What is the benefit of using half-cycle-path?

What is the procedure for timing ECOs? What are the timing fix techniques?

After PnR netlist is ready, STA engineers needs to do timing verification and perform timing ECO as needed. In this post, we will cover the timing ECO procedure, and some common timing fix techniques. A typical timing ECO procedure is shown in the diagram below:

Timing ECO Procedure

Continue reading → What is the procedure for timing ECOs? What are the timing fix techniques?

How to calculate timing slack using OCV

In previous post, we talked about the concepts of OCV, AOCV and POCV. In this post, we will use an example to further illustrate how to calculate timing slack using OCV.

An Example

Let’s assume OCV will derate 10% for clock cells, and 20% for data path. An reg-to-reg path along with delay values is shown in the diagram below.

Timing Slack with Derate

Continue reading → How to calculate timing slack using OCV

What are setup time and hold time?

When clock start rising, the outputs might start to change after the clock-to-q contamination delay, known as tccq and shall absolutely settle down to the stable value within the clock-to-q propagation delay, tpcq. They represent the shortest and longest delays through the circuit. In order for a circuit to sample its input correctly, the inputs must be stabilized at least some setup time, tsetup, before the rising edge of the clock and shall remain stable for at least hold time, thold.

The definition of setup time and hold time is often asked in hardware interviews. We recommend readers to memorize the definition. In next post, we will cover the setup time and hold time constraints.