What to check before running synthesis?

We discussed a general DC synthesis flow in previous post, and there are several things we need to check before actually running “compile_ultra”:

  1. Design should be fully read in by DC, and there shall be no black boxes or missing libraries
  2. Review linting issues, for example, no unexpected undriven inputs and outputs without loading, no bit width mismatch, no wire loop, no combo loop, etc.
  3. The SDC needs to be loaded correctly by DC, for example, use “report_timing_requirements -ignored” to check for invalid exceptions
  4. The SDC needs to be complete, for example, there is no missing clock, no un-clocked registers, no unconstrained ports, etc. Use “check_timing” command to check the completeness of SDC
  5. Optionally, designers can direct DC not to use ULVT / ELVT cells. This leaves more timing margin in place and route

Designers should check all listed items above, in order to get good synthesis results.

In some companies, such checks are performed automatically, and any error or warning will be captured in dashboards.

What are the common DC synthesis optimization techniques?

We have covered the basic DC synthesis flow in previous post. In synthesis, there are a couple of techniques that can help us improve the synthesis results:

Apply optimization directives as needed or as applicable
Apply appropriate compile options
Use path groups to apply more focus on critical paths
Incremental compile

Apply Optimization Directives

We listed a few optimization directives below:

  1. High-Effort Timing Optimization: By default it is disabled; To enable it, do “set_app_var compile_timing_high_effort true
  2. Prioritizing setup timing over DRCs: By default DRCs have higher priority than timing during optimization. Otherwise, do “set_cost_priority -delay
  3. Disabling DRC fixes in clock network. Generally clock buffering prior to CTS is not desired; To disable DRC fixing on the entire clock network, do “set_auto_disable_drc_nets -on_clock_network true
  4. Test-ready synthesis is to account for area/timing impact of scan register during synthesis before stitching up scan chains; before synthesis, specify scan scheme by doing “set_scan_configuration -style <multiplexed_flip_flop | clocked_scan | ssd | aux_clock_lssd>”, then do “compile_ultra -incremental -scan
  5. Multi-Core optimization. For example, do “set_host_options -max_cores 4”. To confirm host options, do “report_host_options

Continue reading → What are the common DC synthesis optimization techniques?

What are basic setups before running synthesis? How to do “set_app_var” and create milkyway library?

There are some basic setups before running synthesis. By setting “search_path”, designers do not need to specify the absolute paths of files; Designers needs to specify the target technology library as well as the link library to resolve all instances inside the design.

To run Topographical synthesis / production synthesis, physical data is required. The following example shows how to setup milkyway design library for DC-Topographical.

Continue reading → What are basic setups before running synthesis? How to do “set_app_var” and create milkyway library?