How to implement a home directory for MESI protocol?

In previous post, we briefly discussed some variants of cache coherence protocol. We also pointed out that, in widely adopted NUMA architecture, snoop-based cache coherence scheme is typically combined with home directories associated with each distributed home memory. Although sounds intuitive, there are a couple of home directory implementation issues we need to consider, including

Status tracked by home directory
Non atomic operations

Status Tracked by Home Directory

Home directory can receive read request, write request or invalidate from local cache. For a read or write request, it needs to decide whether the data is in the home memory or in a remote cache; for a write or invalidate request, it needs to invalidate the remote cache blocks. This means, the home directory has to keep track of cache block state, as well as which cache has the cache block copy.

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What are MESI / MEOSI / MEOFSI protocols?

We discussed how MSI protocol works in previous post. However, in practice, other variants of MSI protocol are more commonly used. These includes:

MESI
MEOSI
MEOFSI

MESI Protocol

MESI adds the state Exclusive to be basic MSI protocol, indicating “clean exclusive” state. As a comparison, M state indicates “dirty exclusive” or “modified exclusive” state.

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Can you show the state transition for snoop-based scheme using MSI protocol?

The snoop based scheme is common used in both UMA and NUMA architectures, due to its flexibility and ease of scalability. In this post, we will discuss the state transition for snoop based scheme in both UMA and NUMA architectures. The protocol we are using is MSI protocol, i.e., a cache block can be in modified, shared or invalid state. Continue reading → Can you show the state transition for snoop-based scheme using MSI protocol?

What is cache coherency? How to enforce cache coherency?

In previous post, we discussed the UMA / NUMA architecture. But caching shared data in different processors becomes a new problem. This is because different processors hold their view of memory through their individual caches. Cache coherency plays an important role in avoiding different processors seeing different values for the same data.

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