Write a single Verilog module describing 5-to-1 multiplexer. Write a testbench using -2, -1, 0, 1, 2 for the five inputs of the multiplexer respectively, and apply appropriate values to the select lines to pass these inputs to the output.
Parameterized port list is used for making the parameterized modules. Instead of designing the module with fixed port length.
The outputs of Moore Machine only depends on the current state of the system circuit while the outputs of Mealy Machine depends on both the current state of the circuit and the inputs.
Blocking assignments/statements are used to create combinatorial logic which are written as “=” operator. Non-blocking assignments/statements are used to create sequential logic, which are written as “<=” operator. The registers/wire on the left side of blocking assignments are updated immediately while the registers/wire on the left side of non-blocking assignments are updated in the next clock cycle.