How to specify SGDC / CDC constraints?

Before running Spyglass CDC flow, we need to provide some inputs to Spyglass. One of the most important inputs is SGDC constraints. Usually, in SGDC constraints, designers are required to specify:

  1. Current design, to limit the scope of CDC check
  2. List of source clocks and generated clocks
  3. List of valid abstract port / input constraints. Designers can derive these constraints from SDC such as “set_input_delay
  4. List of valid output constraints. Designers can derive these constraints from SDC such as “set_output_delay
  5. List of valid clock groups constraints. Designers can derive these constraints from SDC such as “set_clock_group”. Unlike STA, CDC flow by default assumes all clocks are asynchronous to each other, and it will attempt perform CDC check against all clock pairs. Designers shall use “set_clock_groups” to specify which clock pair is synchronous, thus CDC check is not required for such clock pair.

Continue reading → How to specify SGDC / CDC constraints?

How to set generated clock design constraints in Post-CTS run?

We discussed how to set multi-synchronous-clock design constraints, and we will look at how to define clock propagated through sequential logic or macros.

For clocks propagated through sequential logic or macros such as PLL, we need to define generated clocks. The first step, is to define the master clock or the source clock of the generated clock:

Continue reading → How to set generated clock design constraints in Post-CTS run?

How to set single-clock design constraints in Post-CTS run?

In previous post, we introduced how to manipulate objects in SDC. In this post, we will look at how to constrain single-clock design in physical design, or Post-CTS run. Note, there are some differences about how to set single-clock constraints in synthesis, or Pre-CTS run, and we will cover this topic in another post. Interviewees should not mix Pre-CTS and Post-CTS clock constraints.

First, we define the clock and its associated attributes, including clock period, waveform, name, and clock ports. If the clock duty cycle is not 50%, and both negedge and posedge are used in the design, then defining clock waveform is critical. This step is the same between Pre-CTS and Post-CTS run.

Continue reading → How to set single-clock design constraints in Post-CTS run?

How to set single-clock design constraints in Pre-CTS run?

In previous post, we introduced how to manipulate objects in SDC. In this post, we will look at how to constrain single-clock design in synthesis, or Pre-CTS run. Note, there are some differences about how to set single-clock constraints in PnR, or Post-CTS run, and we will cover this topic in another post. Interviewees should not mix Pre-CTS and Post-CTS clock constraints.

First, we define the clock and its associated attributes, including clock period, waveform, name, and clock ports. If the clock duty cycle is not 50%, and both negedge and posedge are used in the design, then defining clock waveform is critical. This step is the same between Pre-CTS and Post-CTS run.

Continue reading → How to set single-clock design constraints in Pre-CTS run?