The snoop based scheme is common used in both UMA and NUMA architectures, due to its flexibility and ease of scalability. In this post, we will discuss the state transition for snoop based scheme in both UMA and NUMA architectures. The protocol we are using is MSI protocol, i.e., a cache block can be in modified, shared or invalid state. Continue reading → Can you show the state transition for snoop-based scheme using MSI protocol?
In previous post, we discussed the UMA / NUMA architecture. But caching shared data in different processors becomes a new problem. This is because different processors hold their view of memory through their individual caches. Cache coherency plays an important role in avoiding different processors seeing different values for the same data.