What are the differences between sync and async reset?

Synchronous reset has the following characteristics:

  1. It will not work if clock path has failures
  2. It tends to immune to glitches, since sync reset requires clock toggling
  3. It makes STA simpler and the whole design synchronous, since sync reset has no difference from regular data path
  4. Sync reset implementation will add a MUX at the input of each flop

Continue reading → What are the differences between sync and async reset?

What are common CDC considerations to transfer a pulse and to transfer multi-bit signals?

CDC considerations to transfer a pulse

Transfer a pulse from slow to fast clock domain, and from fast to slow clock domain, require separate handling.

Generally speaking, passing a signal from slow clock to fast clock is not a problem, since the loss of a pulse is less likely to happen. Based on Nyquist Theorem, if receiving clock frequency is at least 2x of sending clock frequency, then there will be no sampling loss.

Continue reading → What are common CDC considerations to transfer a pulse and to transfer multi-bit signals?

What are common RDC techniques / schemes?

We discussed RDC check in previous post. In this post, we will cover some common RDC techniques that help to avoid RDC violations:

  1. If the destination flop is a synchronizer, then this RDC path can immune from metastability
  2. If the destination flop is clock gated when reset to source flop is asserted, then there will be no metastability issues
  3. If the destination flop is already under reset when source flop is under reset, then there will be no RDC issues
  4. If the destination flop is power down when source flop is under reset, then there will be no RDC issues
  5. If the write enable of the destination flop is 0 when source flop is under reset, then RDC issue can be avoided.
  6. If the source flop output already stays at reset value and is stable when reset asserts, then there will be no RDC violations in destination flop

Continue reading → What are common RDC techniques / schemes?

What does STA do? What does “synchronous” mean?

What is STA?

Static Timing Analysis, a.k.a., STA, is timing verification methodology.

STA is exhaustive, since it uses formal, mathematical techniques instead of dynamic logic simulation, to perform analysis. STA will first identify all timing paths inside the design, and perform timing checks on all paths.

STA is also constraint driven, i.e., by default, it does not report a path that is not constrained for timing.

Unlike CDC, STA assumes all clocks and all paths are synchronous by default, and it will attempt to close timing for all synchronous paths. Designers need to specify asynchronous clocks or paths, where timing closure is not required.

Continue reading → What does STA do? What does “synchronous” mean?

Design an asynchronous FIFO with non-power-of-2 even number of entries

Designing a power-of-2-entry async FIFO is straightforward, but how about designing an async FIFO with non-power-of-2 but even number of entries, for example, 6?

The only difficult part is non power of 2 number gray encoding. For power of 2 number is pretty straightforward. Let’s take 8 for example, the gray code can be:

000 -> 001 -> 011 -> 010 -> 110 -> 111 -> 101 -> 100

Notice that it’s mirror symmetric. To get gray encoding for 6, we can take the middle 2 encoding out of the sequence:

000 -> 001 -> 011 -> 111 -> 101 -> 100

It still satisfies gray encoding. Done!