What is the benefit of using half-cycle-path?

Until now, we focus on the timing of one-cycle-path or full-cycle-path. Sometimes, there may exist half-cycle-path in design. One example will be the launch flop is negedge triggered, while the capture flop is still posedge triggered.

We discussed the clock skew and how it affects STA in previous post. Equivalently, half-cycle-path can be modeled as one-cycle-path with clock skew δ = +T/2. It is obvious that hold time closure is easier while setup time closure is harder for half-cycle-path.

You may wonder what is the benefit of using half-cycle-path in the design.

Continue reading → What is the benefit of using half-cycle-path?

What are the differences between sync and async reset?

Synchronous reset has the following characteristics:

  1. It will not work if clock path has failures
  2. It tends to immune to glitches, since sync reset requires clock toggling
  3. It makes STA simpler and the whole design synchronous, since sync reset has no difference from regular data path
  4. Sync reset implementation will add a MUX at the input of each flop

Continue reading → What are the differences between sync and async reset?

What is ZWL synthesis / sanity synthesis?

Why Do Designers Run Sanity Synthesis?

Before RTL designer hands the design over to synthesis / integration engineer, it will be a good idea to run some sanity synthesis. This is to make sure there is no lint errors, and no timing violations that can make timing closure impossible. We will cover more what to check before running synthesis in next post.

Sometimes people refer sanity synthesis to be Zero-Wire-Load / ZWL synthesis as well. Before looking at ZWL, it is worthy of understanding Wire Load Model.

Continue reading → What is ZWL synthesis / sanity synthesis?