What is the benefit of using half-cycle-path?

Until now, we focus on the timing of one-cycle-path or full-cycle-path. Sometimes, there may exist half-cycle-path in design. One example will be the launch flop is negedge triggered, while the capture flop is still posedge triggered.

We discussed the clock skew and how it affects STA in previous post. Equivalently, half-cycle-path can be modeled as one-cycle-path with clock skew δ = +T/2. It is obvious that hold time closure is easier while setup time closure is harder for half-cycle-path.

You may wonder what is the benefit of using half-cycle-path in the design.

Continue reading → What is the benefit of using half-cycle-path?

What are the differences between sync and async reset?

Synchronous reset has the following characteristics:

  1. It will not work if clock path has failures
  2. It tends to immune to glitches, since sync reset requires clock toggling
  3. It makes STA simpler and the whole design synchronous, since sync reset has no difference from regular data path
  4. Sync reset implementation will add a MUX at the input of each flop

Continue reading → What are the differences between sync and async reset?

What is ZWL synthesis / sanity synthesis?

Why Do Designers Run Sanity Synthesis?

Before RTL designer hands the design over to synthesis / integration engineer, it will be a good idea to run some sanity synthesis. This is to make sure there is no lint errors, and no timing violations that can make timing closure impossible. We will cover more what to check before running synthesis in next post.

Sometimes people refer sanity synthesis to be Zero-Wire-Load / ZWL synthesis as well. Before looking at ZWL, it is worthy of understanding Wire Load Model.

Continue reading → What is ZWL synthesis / sanity synthesis?

How to set mutually exclusive synchronous clock design constraints?

If there exists mutually exclusive synchronous clocks in the design, designers have several ways to specify the exclusivity of the clocks:

set_case_analysis
set_false_path
set_clock_groups -logically_exclusive
set_clock_groups -physically_exclusive

“set_case_analysis” is the most straightforward way, and it constrains which clock will propagate through. However, it leads to different timing modes, and increases tool total runtime.

For false paths or “exclusive” clock paths, DC will not optimize timing for them, and STA will not check timing for them either.

“set_false_path” is usually not preferred, since it can introduce undesired timing exceptions. False path still impacts the SI analysis.

“set_clock_groups” is the most recommended one, but there are some differences between “-logically_exclusive” and “-physically_exclusive”. “-physically exclusive” does not consider SI effect, while “-logically_exclusive” does.

Continue reading → How to set mutually exclusive synchronous clock design constraints?

How to set generated clock design constraints in Post-CTS run?

We discussed how to set multi-synchronous-clock design constraints, and we will look at how to define clock propagated through sequential logic or macros.

For clocks propagated through sequential logic or macros such as PLL, we need to define generated clocks. The first step, is to define the master clock or the source clock of the generated clock:

Continue reading → How to set generated clock design constraints in Post-CTS run?

How to set generated clock design constraints in Pre-CTS run?

We discussed how to set multi-synchronous-clock design constraints, and we will look at how to define clock propagated through sequential logic or macros.

For clocks propagated through sequential logic or macros such as PLL, we need to define generated clocks. The first step, is to define the master clock or the source clock of the generated clock:

Continue reading → How to set generated clock design constraints in Pre-CTS run?