What is the benefit of using half-cycle-path?

Until now, we focus on the timing of one-cycle-path or full-cycle-path. Sometimes, there may exist half-cycle-path in design. One example will be the launch flop is negedge triggered, while the capture flop is still posedge triggered.

We discussed the clock skew and how it affects STA in previous post. Equivalently, half-cycle-path can be modeled as one-cycle-path with clock skew δ = +T/2. It is obvious that hold time closure is easier while setup time closure is harder for half-cycle-path.

You may wonder what is the benefit of using half-cycle-path in the design.

Continue reading → What is the benefit of using half-cycle-path?

What are the differences between sync and async reset?

Synchronous reset has the following characteristics:

  1. It will not work if clock path has failures
  2. It tends to immune to glitches, since sync reset requires clock toggling
  3. It makes STA simpler and the whole design synchronous, since sync reset has no difference from regular data path
  4. Sync reset implementation will add a MUX at the input of each flop

Continue reading → What are the differences between sync and async reset?

What are universal gates?

A universal gate is a gate or a group of gates which can implement any Boolean function without the need to use any other types of gates.

Universal gates satisfy 2 conditions:

    1. They should be able to block the input propagation. For example, if one input of an AND gate is 0, then the output of the AND gate stays at 0, i.e., the other input is blocked
    2. They should be able to form an inverter. For example, if both inputs of a NAND gate are tied to the same value, the output of the NAND gate will be inverted, i.e., NAND gate can form an inverter

Continue reading → What are universal gates?

What is Conformal LEC flow? How does Conformal LEC perform key point mapping?

We already discussed why designers need to do LEC, and we will talk about Conformal LEC flow in this post.

In LEC setup, there are several steps that designers need to follow:

    • Read and elaborate reference design
    • Read and elaborate revised design
    • Specify “notranslate modules” for blackboxing if the module is a macro, or the module has been LECed in block level
    • Set certain constraints, for example, when comparing between RTL and synthesis netlist, set case analysis to ignore scan ports

Continue reading → What is Conformal LEC flow? How does Conformal LEC perform key point mapping?

What is LEC? Why should we do LEC?

Logical Equivalence Check, or LEC, is a formal verification method, to compare revised design with reference design. There are several circumstances where LEC is required, for example:

  1. Designers need to compare synthesis netlist (revised design) with RTL (reference design), to make sure synthesis optimization and scan insertion do not alter designers’ intent
  2. Physical designers need to compare PnR netlist (revised design) with synthesis netlist (reference design), to make sure the PnR results and timing ECOs do not change synthesis netlist functionalities
  3. Designers may perform ECOs for new feature addition and bug fix. There should not be any mismatch between ECOed RTL and synthesis netlist

The most common LEC tools include Cadence Conformal LEC, and Synopsys Formality. We will focus on Cadence Conformal LEC flow from next post.

What to check before running synthesis?

We discussed a general DC synthesis flow in previous post, and there are several things we need to check before actually running “compile_ultra”:

  1. Design should be fully read in by DC, and there shall be no black boxes or missing libraries
  2. Review linting issues, for example, no unexpected undriven inputs and outputs without loading, no bit width mismatch, no wire loop, no combo loop, etc.
  3. The SDC needs to be loaded correctly by DC, for example, use “report_timing_requirements -ignored” to check for invalid exceptions
  4. The SDC needs to be complete, for example, there is no missing clock, no un-clocked registers, no unconstrained ports, etc. Use “check_timing” command to check the completeness of SDC
  5. Optionally, designers can direct DC not to use ULVT / ELVT cells. This leaves more timing margin in place and route

Designers should check all listed items above, in order to get good synthesis results.

In some companies, such checks are performed automatically, and any error or warning will be captured in dashboards.