Inter-Integrated Circuit

The I2C is a multi-leader, multi-follower, serial communication protocol between digital devices. In this section, we will cover the working principles of the I2C in terms of the data format, connection diagram, and transmission and reception operations.

Data Format

In the I2C, every follower has a unique address. Data transfer starts with this address. When the follower wakes up and acknowledges back the leader, transfer continues with the pointer/address and data or directly data is transferred depending on the protocol. The address of a follower is usually composed of seven bits. However, in some cases the address can be either eight or ten bits. Independent of the address, pointer, and data size, the transfer is performed in terms of eight-bit packages. Each package has seven-bit address, pointer, and data and one-bit acknowledge value. The receiver merges packet to extract data.

Connection Diagram

The I2C data bus has two wires called serial data line (SDA) and serial clock line (SCL). Besides, all connected devices need a common ground and power line. As a result, the I2C will need four wires for communication. The connection diagram of a generic I2C is presented as https://www.analog.com/-/media/analog/en/landing-pages/technical-articles/i2c-primer-what-is-i2c-part-1-/36684.png?la=en&w=900 . The SDA and SCL are bidirectional lines. Both the lines are connected to VDD by a pull-up resistor. This means they are at logic level 1 when idle. Different from the SPI, every follower has a unique address in the I2C. Therefore, the follower and leader can be chosen over the serial data line without the need of a select signal. Thus, other than power and ground signals, the I2C bus has only two wires connected to all devices. This advantage saves the pin usage compared to the SPI.

Transmission and Reception Operations

As mentioned in the previous section, data on the I2C communication is carried by eight-bit packages. The leader starts the transmission by sending the follower address and read/write decision bit. The follower with this address on the network wakes up and acknowledges the leader that it is alive and ready to talk. Then depending on the decision bit, the leader writes or reads data from the follower. The leader ends the talk by sending a stop signal. The following figure shows the complete timing diagram of the I2C communication: https://www.analog.com/-/media/analog/en/landing-pages/technical-articles/i2c-primer-what-is-i2c-part-1-/36685.png?la=en&w=900, The leader starts transmission by a logic level 1 to 0 transition on SDA while SCL stays at logic level 1. We can call this as the start signal. The transmission ends by a logic level 0 to 1 transition on the SDA while SCL is at logic level 1. We can call this as the stop signal. The address of the device and data is transmit address of the follower. Then R/W signal is sent, which tells the follower if the leader is going to read of write the data to/from the follower. Next, the leader starts sending or receiving data (with the MSB first) followed by an acknowledge signal. There are no restrictions on the number of successively transmitted data bits. The communication continues until the leader sends the stop signal. Note that during the acknowledge signal the transmitter releases the SDA line and the receiver pulls the line to logic level 0 while SCL is at logic level 1.

 

 

What is the benefit of using half-cycle-path?

Until now, we focus on the timing of one-cycle-path or full-cycle-path. Sometimes, there may exist half-cycle-path in design. One example will be the launch flop is negedge triggered, while the capture flop is still posedge triggered.

We discussed the clock skew and how it affects STA in previous post. Equivalently, half-cycle-path can be modeled as one-cycle-path with clock skew δ = +T/2. It is obvious that hold time closure is easier while setup time closure is harder for half-cycle-path.

You may wonder what is the benefit of using half-cycle-path in the design.

Continue reading → What is the benefit of using half-cycle-path?

What are the differences between sync and async reset?

Synchronous reset has the following characteristics:

  1. It will not work if clock path has failures
  2. It tends to immune to glitches, since sync reset requires clock toggling
  3. It makes STA simpler and the whole design synchronous, since sync reset has no difference from regular data path
  4. Sync reset implementation will add a MUX at the input of each flop

Continue reading → What are the differences between sync and async reset?

What are universal gates?

A universal gate is a gate or a group of gates which can implement any Boolean function without the need to use any other types of gates.

Universal gates satisfy 2 conditions:

    1. They should be able to block the input propagation. For example, if one input of an AND gate is 0, then the output of the AND gate stays at 0, i.e., the other input is blocked
    2. They should be able to form an inverter. For example, if both inputs of a NAND gate are tied to the same value, the output of the NAND gate will be inverted, i.e., NAND gate can form an inverter

Continue reading → What are universal gates?

What is Conformal LEC flow? How does Conformal LEC perform key point mapping?

We already discussed why designers need to do LEC, and we will talk about Conformal LEC flow in this post.

In LEC setup, there are several steps that designers need to follow:

    • Read and elaborate reference design
    • Read and elaborate revised design
    • Specify “notranslate modules” for blackboxing if the module is a macro, or the module has been LECed in block level
    • Set certain constraints, for example, when comparing between RTL and synthesis netlist, set case analysis to ignore scan ports

Continue reading → What is Conformal LEC flow? How does Conformal LEC perform key point mapping?