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What are setup time and hold time?

When clock start rising, the outputs might start to change after the clock-to-q contamination delay, known as tccq and shall absolutely settle down to the stable value within the clock-to-q propagation delay, tpcq. They represent the shortest and longest delays through the circuit. In order for a circuit to sample its input correctly, the inputs must be stabilized at least some setup time, tsetup, before the rising edge of the clock and shall remain stable for at least hold time, thold.

The definition of setup time and hold time is often asked in hardware interviews. We recommend readers to memorize the definition. In next post, we will cover the setup time and hold time constraints.