How Computers Work?
What if you got ask the very basic question: How Computers Work?
A brief answer:
A more comprehensive answer:
Round-Robin Arbiter: The Wrong Design and The Right Design
Although it is simple, fixed priority arbiters may cause starvation across different requests. To guarantee fairness, designers usually use round-robin arbiter. We will start from a wrong design, in order to enhance your understanding of round-robin; then we will cover the right design, that can guarantee fairness under all conditions.
The Wrong Round-Robin Arbiter Design
Assume the design takes 3 requests, i.e., req[2:0].
Internally, this design keeps a 3-bit history array, i.e., token[2:0]. Token[2:0] is a one-hot array initialized to 3’b001, and it circular left shifts 1 bit every time there are valid requests. The way the design works:
- If token[2:0] == 3’b001, then req[0] has highest priority while req[2] has the lowest priority;
- If token[2:0] == 3’b010, then req[1] has highest priority while req[0] has lowest priority;
- If token[2:0] == 3’b100, then req[2] has highest priority while req[1] has the lowest priority
The Verilog code is shown below.
Continue reading → Round-Robin Arbiter: The Wrong Design and The Right Design
Tell us about the different performance characterization criterion between RTL design and HLS design
Interviewers often ask about the key criterions which are used to characterize different RTL and HLS designs if your are on an HLS interview.
What is FPGA Design Process?
Due to the complexity and magnitude of state-of-the-art FPGAs, we as designers started imposing a higher-level structure on building designs. In turns that FPGAs designs and implementations are often composed of different cores or IP modules.
What are the shortcomings/limitations of High Level Synthesis?
Though High Level Synthesis (HLS) is like using a more software way to realize hardware design needs, there are multiple fundamentals which are common in software development are not exist in HLS.
Continue reading → What are the shortcomings/limitations of High Level Synthesis?
What is High Level Synthesis?
Generally speaking, High-level synthesis (HLS) is a kind of abstraction which enables a chip/circuit design engineer to focus on overview of a large architectural problems instead of register level or cycle-to-cycle operating problems.
