Although it is simple, fixed priority arbiters may cause starvation across different requests. To guarantee fairness, designers usually use round-robin arbiter. We will start from a wrong design, in order to enhance your understanding of round-robin; then we will cover the right design, that can guarantee fairness under all conditions.

The Wrong Round-Robin Arbiter Design

Assume the design takes 3 requests, i.e., req[2:0].

Internally, this design keeps a 3-bit history array, i.e., token[2:0]. Token[2:0] is a one-hot array initialized to 3’b001, and it circular left shifts 1 bit every time there are valid requests. The way the design works:

1. If token[2:0] == 3’b001, then req[0] has highest priority while req[2] has the lowest priority;
2. If token[2:0] == 3’b010, then req[1] has highest priority while req[0] has lowest priority;
3. If token[2:0] == 3’b100, then req[2] has highest priority while req[1] has the lowest priority

The Verilog code is shown below.

Continue reading → Round-Robin Arbiter: The Wrong Design and The Right Design