Synchronous reset has the following characteristics:

1. It will not work if clock path has failures
2. It tends to immune to glitches, since sync reset requires clock toggling
3. It makes STA simpler and the whole design synchronous, since sync reset has no difference from regular data path
4. Sync reset implementation will add a MUX at the input of each flop

Continue reading → What are the differences between sync and async reset?