Inter-Integrated Circuit

The I2C is a multi-leader, multi-follower, serial communication protocol between digital devices. In this section, we will cover the working principles of the I2C in terms of the data format, connection diagram, and transmission and reception operations.

Data Format

In the I2C, every follower has a unique address. Data transfer starts with this address. When the follower wakes up and acknowledges back the leader, transfer continues with the pointer/address and data or directly data is transferred depending on the protocol. The address of a follower is usually composed of seven bits. However, in some cases the address can be either eight or ten bits. Independent of the address, pointer, and data size, the transfer is performed in terms of eight-bit packages. Each package has seven-bit address, pointer, and data and one-bit acknowledge value. The receiver merges packet to extract data.

Connection Diagram

The I2C data bus has two wires called serial data line (SDA) and serial clock line (SCL). Besides, all connected devices need a common ground and power line. As a result, the I2C will need four wires for communication. The connection diagram of a generic I2C is presented as https://www.analog.com/-/media/analog/en/landing-pages/technical-articles/i2c-primer-what-is-i2c-part-1-/36684.png?la=en&w=900 . The SDA and SCL are bidirectional lines. Both the lines are connected to VDD by a pull-up resistor. This means they are at logic level 1 when idle. Different from the SPI, every follower has a unique address in the I2C. Therefore, the follower and leader can be chosen over the serial data line without the need of a select signal. Thus, other than power and ground signals, the I2C bus has only two wires connected to all devices. This advantage saves the pin usage compared to the SPI.

Transmission and Reception Operations

As mentioned in the previous section, data on the I2C communication is carried by eight-bit packages. The leader starts the transmission by sending the follower address and read/write decision bit. The follower with this address on the network wakes up and acknowledges the leader that it is alive and ready to talk. Then depending on the decision bit, the leader writes or reads data from the follower. The leader ends the talk by sending a stop signal. The following figure shows the complete timing diagram of the I2C communication: https://www.analog.com/-/media/analog/en/landing-pages/technical-articles/i2c-primer-what-is-i2c-part-1-/36685.png?la=en&w=900, The leader starts transmission by a logic level 1 to 0 transition on SDA while SCL stays at logic level 1. We can call this as the start signal. The transmission ends by a logic level 0 to 1 transition on the SDA while SCL is at logic level 1. We can call this as the stop signal. The address of the device and data is transmit address of the follower. Then R/W signal is sent, which tells the follower if the leader is going to read of write the data to/from the follower. Next, the leader starts sending or receiving data (with the MSB first) followed by an acknowledge signal. There are no restrictions on the number of successively transmitted data bits. The communication continues until the leader sends the stop signal. Note that during the acknowledge signal the transmitter releases the SDA line and the receiver pulls the line to logic level 0 while SCL is at logic level 1.

 

 

Why is there no possible performance improvement with cache upsizing?

Usually, with cache upsizing, we expect to see system performance improvement. However, this is not always the case. There could be several reasons:

  1. The “compulsory”, instead of “capacity”, prevents the performance improvement from cache upsizing. This means the temporal locality and spatial locality offered by cache are not utilized. For example, the program keeps to access new data and there is no data reuse, which can happen in streaming applications; if context switch happens often, then cache flush may happen often and more “compulsory” will occur

  2. In cache-coherent system, there may be 2 caches competing for one copy of data, i.e., “coherence” miss. This can happen when 2 CPUs want to gain the lock or semaphore simultaneously. Increasing cache size will not help performance in this case
  3. Assuming the cache upsizing is achieved by cache line upsizing, then the loading time of a cache line will increase. This in turn increases the cache miss penalty and average memory access time
  4. Assuming the cache upsizing is achieved by increasing associativity, then the hit latency as well as average memory access time may increase. This is because physical implementation of high associativity cache can be hard

Continue reading → Why is there no possible performance improvement with cache upsizing?

What is functional coverage? How to write functional coverage?

100% code coverage does not imply the completeness of verification. A fundamental limitation of code coverage is, it does not consider design specs and event sequences. Functional coverage is used address this limitation.

There are 2 ways to measure functional coverage. The first one is called covergroups, which is usually defined by DV engineers in test bench. See this post for more details.

The second one is called cover property, which is defined by designers. Usually cover properties can be specified inline with RTL, or in a separate file bind to RTL. Unlike assert property, cover property can be used to determine whether or not certain aspects of the designs functionality have been exercised. See this post for how to write cover properties.