LeetCode for Hardware Engineering, ASIC/FPGA/VLSI Digital Design and Verification Engineer
Interviewers often ask how to design a memory controller in technical interviews. We show one example below.
The memory controller takes incoming requests along with address and request ID as inputs. It is expected to provide read responses along with response ID as outputs. Internally, it can access memory to fetch the read data.
Continue reading → How to design a memory controller with in-order read responses?
100% code coverage does not imply the completeness of verification. A fundamental limitation of code coverage is, it does not consider design specs and event sequences. Functional coverage is used address this limitation.
There are 2 ways to measure functional coverage. The first one is called covergroups, which is usually defined by DV engineers in test bench. See this post for more details.
The second one is called cover property, which is defined by designers. Usually cover properties can be specified inline with RTL, or in a separate file bind to RTL. Unlike assert property, cover property can be used to determine whether or not certain aspects of the designs functionality have been exercised. See this post for how to write cover properties.
Code coverage is a fundamental DV metric, and it measures how well the RTL code is covered by test bench. Code coverage includes the following aspects:
We recommend readers to refer to this post for more details.
Verilog uses “x” to model the unknown state, but it also introduces potential issues.
The simulation semantics of conditional constructs in Verilog, are not accurate enough to model the ambiguity inherent in un-initialized registers and power on reset values. When the unknown states that are modeled as ‘X’ values become control expressions, these issues are particularly problematic.
In this post, we will cover several techniques to detect and resolve x-related issues in RTL, including:
Jasper Reset
SystemVerilog Assertions / SVA
Gate Level Simulation
X-propagation in RTL Simulation
Continue reading → How to detect and resolve x-related issues in RTL?
SVA is an important formal verification tool, that should be mastered by both designer and verification engineers.
Doulos has a page, perfectly illustrate how to write SVAs. We recommend interviewees to fully digest the content in that page.
In addition, SystemVerilog provides various of built-in methods, to aid and simplify SVA writing. We recommend interviewees to refer to this page.
Most likely this would be the follow-up questions after CDC questions (Fast-to-Slow, Slow-to-Fast). However, the classic double flip-flop sync mechanism mentioned before is not appropriate to be used here.
Continue reading → How to synchronize a multi-bits data bus?
In previous post, we briefly discussed some variants of cache coherence protocol. We also pointed out that, in widely adopted NUMA architecture, snoop-based cache coherence scheme is typically combined with home directories associated with each distributed home memory. Although sounds intuitive, there are a couple of home directory implementation issues we need to consider, including
Status tracked by home directory
Non atomic operations
Home directory can receive read request, write request or invalidate from local cache. For a read or write request, it needs to decide whether the data is in the home memory or in a remote cache; for a write or invalidate request, it needs to invalidate the remote cache blocks. This means, the home directory has to keep track of cache block state, as well as which cache has the cache block copy.
Continue reading → How to implement a home directory for MESI protocol?
