What is the benefit of using half-cycle-path?

Until now, we focus on the timing of one-cycle-path or full-cycle-path. Sometimes, there may exist half-cycle-path in design. One example will be the launch flop is negedge triggered, while the capture flop is still posedge triggered.

We discussed the clock skew and how it affects STA in previous post. Equivalently, half-cycle-path can be modeled as one-cycle-path with clock skew δ = +T/2. It is obvious that hold time closure is easier while setup time closure is harder for half-cycle-path.

You may wonder what is the benefit of using half-cycle-path in the design.

Continue reading → What is the benefit of using half-cycle-path?

What are the differences between sync and async reset?

Synchronous reset has the following characteristics:

  1. It will not work if clock path has failures
  2. It tends to immune to glitches, since sync reset requires clock toggling
  3. It makes STA simpler and the whole design synchronous, since sync reset has no difference from regular data path
  4. Sync reset implementation will add a MUX at the input of each flop

Continue reading → What are the differences between sync and async reset?

What are universal gates?

A universal gate is a gate or a group of gates which can implement any Boolean function without the need to use any other types of gates.

Universal gates satisfy 2 conditions:

    1. They should be able to block the input propagation. For example, if one input of an AND gate is 0, then the output of the AND gate stays at 0, i.e., the other input is blocked
    2. They should be able to form an inverter. For example, if both inputs of a NAND gate are tied to the same value, the output of the NAND gate will be inverted, i.e., NAND gate can form an inverter

Continue reading → What are universal gates?

Design a circuit that detects if one input is a delayed version of the other

Assuming 1b input A is generated by a random sequence, 1b input B is a delayed version of A. The delay value varies, and can be [1, 10] (inclusive).

Design a circuit, that takes A and B as inputs, and Y as output. If B is guaranteed to have 1s, then Y should be 1.

Continue reading → Design a circuit that detects if one input is a delayed version of the other

Design a 4-phase REQ-ACK CDC handshake sender and receiver module

Assuming sender block uses clk1, while receiving block uses clk2. Sender block and receiving block use 4-phase REQ-ACK protocol for clock domain crossing.

Also assume the sender block interacts with its upstream logic using valid-ready protocol, and the receiving block interacts with its downstream logic using valid-ready protocol.

Obviously, 4-phase REQ-ACK protocol is slower than 2-phase REQ-ACK protocol, since each transfer involves 4 signal transitions compared to 2 signal transitions.

However, 4-phase REQ-ACK protocol is more robust than 2-phase REQ-ACK protocol. We will explain the reason in next post.

 

How to identify which bit of the 32b register has stuck-at fault?

Assume a 32-bit write-only register resides in a black box module. As a silicon validation engineer, you have write access to the register through the 32-bit configuration bus, but you do not have read access. Instead, you know what is the bit-XOR value of all 32 bits from the black box. If there is a random bit of the register that has a stuck-at fault, how can you identify which bit has the fault?

Linear Search

The simplest approach is the linear search. In the 1st step, you can write 32’h0000_0001 to the register and get the bit-XOR value, and then write 32’h0000_0000 and get the bit-XOR value again. All possible read values are shown in the table below:

Continue reading → How to identify which bit of the 32b register has stuck-at fault?