This is probably one of most frequently asked Digital/FPGA design interview questions. As we know, FIFO is usually used to buffer/queue data in a system block. So, as a design engineer, we need to decide what’s the minimal depth of the FIFO for the certain case.
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If you’re familiar with SRAM structure, for the same amount storage, dual-port SRAM takes more area than single-port SRAM, since each dual-port SRAM row needs 2 word lines. If we were to use single-port SRAM as FIFO memory storage, the area can be further reduced.