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How to implement precise interrupt?

In previous post, we discussed the definition of precise interrupt. In this post, we will cover the implementations, based on J.E. Smith and A.R. Pleszkun’s paper Implementing Precise Interrupt in Pipelined Processor.

A total of 4 approaches will be discussed:

Result shift register
Reorder buffer with bypass
History buffer
Future file

Continue reading → How to implement precise interrupt?