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Case statement is usually used to model read-only memory (ROM). For some compiler or certain device family, either the address or the output has to be registered for ROM code to be inferred. block RAM resources could be used to implemented ROMs with synchronous outputs or address inputs.
In previous post, we discussed the definition of precise interrupt. In this post, we will cover the implementations, based on J.E. Smith and A.R. Pleszkun’s paper Implementing Precise Interrupt in Pipelined Processor.
A total of 4 approaches will be discussed:
Result shift register
Reorder buffer with bypass
From CPU’s perspective, the most important metric to measure cache performance is average memory access time.
Memory Access Time Definition 1
Average memory access time = cache hit rate x hit latency + (1 – cache hit rate) x miss penalty
Wikipedia has a perfect definition about interrupt:
“In system programming, an interrupt is a signal to the processor emitted by hardware or software indicating an event that needs immediate attention. An interrupt alerts the processor to a high-priority condition requiring the interruption of the current code the processor is executing…”
There are several ways to categorize interrupts, among which the most important one is precise interrupt and imprecise interrupt.
We will discuss the definition about precise interrupt in this post, based on J.E. Smith and A.R. Pleszkun’s paper Implementing Precise Interrupt in Pipelined Processor.