This is probably one of most frequently asked Digital/FPGA design interview questions. As we know, FIFO is usually used to buffer/queue data in a system block. So, as a design engineer, we need to decide what’s the minimal depth of the FIFO for the certain case.
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If the sync FIFO has non-power-of-2 entries, for example, 3 entries, what can we do? Well, we have at least 2 approaches.
The easiest way is to maintain a counter for FIFO occupied entries, and use it to generate the FIFO empty or full condition.
The second approach is to use the same trick for pointer encoding as what we see in power-of-2-entry FIFO. For example, both read and write pointers have (2 + 1) bits, where 2 is for bits to index 3-entry FIFO, and 1 is to decode FIFO full and empty conditions. Pointer value change shall have the following patterns:
000 -> 001 -> 010 -> 100 -> 101 -> 110 -> 000 -> …
When read pointer is equal to write pointer, the FIFO is empty; When read pointer is the same as write pointer other than MSB, the FIFO is full.
Static power is proportional to circuit leakage current and supply voltage Vdd. Thus we have following ways to reduce static power:
- Dynamic Vth scaling by adjusting substrate bias
- Use multi-Vth devices in design
- Use high-Vth device whenever possible
- Dynamic supply voltage scaling
- Use multi-Vdd in design
- Shut off the power in standby mode
Static power is the circuit leakage power. Static power exists even if there is no activities. When power is applied to the transistors, transistors would leak current naturally due to physical characteristics of the silicon and manufacturing defects. Examples of static power include transistor drain to source leakage and silicon substrate leakage.
Dynamic power is the power used to charge or discharge transistor intrinsic capacitor. Dynamic power only exists when signals toggle either from low-to-high or high-to-low. For example, clock toggles every cycle, thus clock paths consumes huge amount of dynamic power if there is no clock gating.
Short-circuit dissipation power occurs when both NMOS and PMOS transistors are active for a small period of time, during which current will find a path directly from power rail to ground. Hence, this creates a short-circuit current. In first-order analysis, we assume 0 transistor rise / fall time during transition, and short-circuit dissipation power can be ignored. However, we shall assume finite transistor transition time in more accurate analysis, thus short-circuit dissipation power exists every time signal toggles.
In previous post, we discussed setup time and hold time definitions. We will cover the basics of STA: setup time and hold time constraints.
These constraints dictate the max and min delays of a computational logic between flip-flops. If any of the constraint is not met, we call it as timing violation. Timing violations lead to metastability.
When clock start rising, the outputs might start to change after the clock-to-q contamination delay, known as tccq and shall absolutely settle down to the stable value within the clock-to-q propagation delay, tpcq. They represent the shortest and longest delays through the circuit. In order for a circuit to sample its input correctly, the inputs must be stabilized at least some setup time, tsetup, before the rising edge of the clock and shall remain stable for at least hold time, thold.
The definition of setup time and hold time is often asked in hardware interviews. We recommend readers to memorize the definition. In next post, we will cover the setup time and hold time constraints.