How Computers Work?
What if you got ask the very basic question: How Computers Work?
A brief answer:
A more comprehensive answer:
Can we arbitrarily increase the CPU pipeline depth?
CPU pipelining is a common technique to increase throughput and instruction level parallelism. Can we arbitrarily increase the CPU pipeline depth? Short answer is NO.
This is an open question. We recommend interviewees to answer this question from the following aspects:
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How to design a memory controller with in-order read responses?
Interviewers often ask how to design a memory controller in technical interviews. We show one example below.
The memory controller takes incoming requests along with address and request ID as inputs. It is expected to provide read responses along with response ID as outputs. Internally, it can access memory to fetch the read data.
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Why is there no possible performance improvement with cache upsizing?
Usually, with cache upsizing, we expect to see system performance improvement. However, this is not always the case. There could be several reasons:
- The “compulsory”, instead of “capacity”, prevents the performance improvement from cache upsizing. This means the temporal locality and spatial locality offered by cache are not utilized. For example, the program keeps to access new data and there is no data reuse, which can happen in streaming applications; if context switch happens often, then cache flush may happen often and more “compulsory” will occur
- In cache-coherent system, there may be 2 caches competing for one copy of data, i.e., “coherence” miss. This can happen when 2 CPUs want to gain the lock or semaphore simultaneously. Increasing cache size will not help performance in this case
- Assuming the cache upsizing is achieved by cache line upsizing, then the loading time of a cache line will increase. This in turn increases the cache miss penalty and average memory access time
- Assuming the cache upsizing is achieved by increasing associativity, then the hit latency as well as average memory access time may increase. This is because physical implementation of high associativity cache can be hard
Continue reading → Why is there no possible performance improvement with cache upsizing?
How to implement w = 3/2 x + 1/4 y + z?
Obviously, w = 3/2 x + 1/4 y + z = x + (x >> 1) + (y >> 2) + z. But, this is not the end of the story.
All variables here need to be interpreted as fixed point number, with lower 2 digits representing 0.5 and 0.25.
Let’s say x, y and z are within the range between 0 and 3, inclusive. Then w is within the range between 0 and 8.25, inclusive. w’s integer part has 4 bits, and w has 6 bits in total.
‘d8.25 can be represented as ‘b1000.01