Serial Peripheral Interface

The serial peripheral interface (SPI) is a digital communication protocol for two or more devices as the UART. Here, we will focus only on the SPI communication between two devices. Hence, one device will be the transmitter and the other receiver. Different from the UART, the SPI is a synchronous communication protocol. Besides, communication between the transmitter and receiver is duplex. In other words, data is transmitted and received at the same time in the SPI. Therefore, the SPI communication uses four wires. Two of these wires are for data transfer. One wire is used for common clock signal (for synchronization). The fourth wire is used to enable (select) signal to be explained later.

Being synchronous, the SPI needs a common clock signal generated by either the transmitter or receiver. Clock generating side is called leader. The other side is called follower. The roles are generally called master and slave in literature. However, we prefer leader and follower naming on our website. Therefore, we will use the terms forward. As a result we can have leader-transmitter, leader-receiver, follower-transmitter, and follower-receiver options.

Working Principles of SPI

The working principles of the SPI are simpler than the UART. To understand them, we introduce the data format, connection diagram, transmission and reception operations, and timing in the following parts.

Data Format

Different from the UART, data packet size is not constant in the SPI. This is an advantage since the user can select the packet size as he or she desires. Moreover, the dedicated common clock and enable signal avoid using start and stop bits in the UART. The only requirement here is the need for determining the data packet size. Hence, the transmitter and receiver can understand each other.

Connection Diagram

The SPI uses a dedicated clock line, two data lines (one for transmitter, one for receiver), and a select (enable) line as mentioned in the previous section. Here, the clock signal is denoted by SCLK. The leader output, follower input is denoted by MOSI. The leader input, follower output is denoted by MISO. Select is denoted by SS which is used byt the leader to wake up the follower. The select line is also used when more than one follower is connected to a single leader.

Transmission and Reception Operations

In the SPI, the data transmission and reception is controlled by the leader through SCLK and SS signals. When there is no transmission, SS stays at logic level 1 and SCLK stays either at logic level 0 or 1 depending on the SPI mode. The modes of the SPI and their timing diagrams will be discussed later. The SPI Communication starts when the leader wakes the follower by setting SS to logic level 0. Next, the leader and follower start interchanging data in every clock cycle set by SCLK. Here either the leader sends a bit through MOSI line or the follower sends a bit through MISO line. The SPI mode also determines if data will be sent on the rising or falling edge of SCLK. After all bits are transferred, the common clock stops and leader deselects and the follower by changing SS to logic level 1.

Inter-Integrated Circuit

The I2C is a multi-leader, multi-follower, serial communication protocol between digital devices. In this section, we will cover the working principles of the I2C in terms of the data format, connection diagram, and transmission and reception operations.

Data Format

In the I2C, every follower has a unique address. Data transfer starts with this address. When the follower wakes up and acknowledges back the leader, transfer continues with the pointer/address and data or directly data is transferred depending on the protocol. The address of a follower is usually composed of seven bits. However, in some cases the address can be either eight or ten bits. Independent of the address, pointer, and data size, the transfer is performed in terms of eight-bit packages. Each package has seven-bit address, pointer, and data and one-bit acknowledge value. The receiver merges packet to extract data.

Connection Diagram

The I2C data bus has two wires called serial data line (SDA) and serial clock line (SCL). Besides, all connected devices need a common ground and power line. As a result, the I2C will need four wires for communication. The connection diagram of a generic I2C is presented as . The SDA and SCL are bidirectional lines. Both the lines are connected to VDD by a pull-up resistor. This means they are at logic level 1 when idle. Different from the SPI, every follower has a unique address in the I2C. Therefore, the follower and leader can be chosen over the serial data line without the need of a select signal. Thus, other than power and ground signals, the I2C bus has only two wires connected to all devices. This advantage saves the pin usage compared to the SPI.

Transmission and Reception Operations

As mentioned in the previous section, data on the I2C communication is carried by eight-bit packages. The leader starts the transmission by sending the follower address and read/write decision bit. The follower with this address on the network wakes up and acknowledges the leader that it is alive and ready to talk. Then depending on the decision bit, the leader writes or reads data from the follower. The leader ends the talk by sending a stop signal. The following figure shows the complete timing diagram of the I2C communication:, The leader starts transmission by a logic level 1 to 0 transition on SDA while SCL stays at logic level 1. We can call this as the start signal. The transmission ends by a logic level 0 to 1 transition on the SDA while SCL is at logic level 1. We can call this as the stop signal. The address of the device and data is transmit address of the follower. Then R/W signal is sent, which tells the follower if the leader is going to read of write the data to/from the follower. Next, the leader starts sending or receiving data (with the MSB first) followed by an acknowledge signal. There are no restrictions on the number of successively transmitted data bits. The communication continues until the leader sends the stop signal. Note that during the acknowledge signal the transmitter releases the SDA line and the receiver pulls the line to logic level 0 while SCL is at logic level 1.



What is the difference between Unified and non-unified shader architectures?

Shader architectures can be unified or non-unified. Many of the mobile and embedded GPUs have unified shader architecture.

  • A unified shader architecture executes shader programs, such as fragment and vertex shaders, on the same processing modules.
  • A non-unified architecture uses separate dedicated processing modules for vertex and fragment processing.

Unified architectures can save power and increase performance compared to a non-unified architecture.

Unified architectures also scale much more easily to a given application, whether it is fragment or vertex shader bound, as the unified processors will be used accordingly.

What is the benefit of using half-cycle-path?

Until now, we focus on the timing of one-cycle-path or full-cycle-path. Sometimes, there may exist half-cycle-path in design. One example will be the launch flop is negedge triggered, while the capture flop is still posedge triggered.

We discussed the clock skew and how it affects STA in previous post. Equivalently, half-cycle-path can be modeled as one-cycle-path with clock skew δ = +T/2. It is obvious that hold time closure is easier while setup time closure is harder for half-cycle-path.

You may wonder what is the benefit of using half-cycle-path in the design.

Continue reading → What is the benefit of using half-cycle-path?

What are the differences between sync and async reset?

Synchronous reset has the following characteristics:

  1. It will not work if clock path has failures
  2. It tends to immune to glitches, since sync reset requires clock toggling
  3. It makes STA simpler and the whole design synchronous, since sync reset has no difference from regular data path
  4. Sync reset implementation will add a MUX at the input of each flop

Continue reading → What are the differences between sync and async reset?

What are universal gates?

A universal gate is a gate or a group of gates which can implement any Boolean function without the need to use any other types of gates.

Universal gates satisfy 2 conditions:

    1. They should be able to block the input propagation. For example, if one input of an AND gate is 0, then the output of the AND gate stays at 0, i.e., the other input is blocked
    2. They should be able to form an inverter. For example, if both inputs of a NAND gate are tied to the same value, the output of the NAND gate will be inverted, i.e., NAND gate can form an inverter

Continue reading → What are universal gates?