What is the benefit of using half-cycle-path?

Until now, we focus on the timing of one-cycle-path or full-cycle-path. Sometimes, there may exist half-cycle-path in design. One example will be the launch flop is negedge triggered, while the capture flop is still posedge triggered.

We discussed the clock skew and how it affects STA in previous post. Equivalently, half-cycle-path can be modeled as one-cycle-path with clock skew δ = +T/2. It is obvious that hold time closure is easier while setup time closure is harder for half-cycle-path.

You may wonder what is the benefit of using half-cycle-path in the design.

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What are the differences between sync and async reset?

Synchronous reset has the following characteristics:

  1. It will not work if clock path has failures
  2. It tends to immune to glitches, since sync reset requires clock toggling
  3. It makes STA simpler and the whole design synchronous, since sync reset has no difference from regular data path
  4. Sync reset implementation will add a MUX at the input of each flop

Continue reading → What are the differences between sync and async reset?

What are universal gates?

A universal gate is a gate or a group of gates which can implement any Boolean function without the need to use any other types of gates.

Universal gates satisfy 2 conditions:

    1. They should be able to block the input propagation. For example, if one input of an AND gate is 0, then the output of the AND gate stays at 0, i.e., the other input is blocked
    2. They should be able to form an inverter. For example, if both inputs of a NAND gate are tied to the same value, the output of the NAND gate will be inverted, i.e., NAND gate can form an inverter

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Design a circuit that detects if one input is a delayed version of the other

Assuming 1b input A is generated by a random sequence, 1b input B is a delayed version of A. The delay value varies, and can be [1, 10] (inclusive).

Design a circuit, that takes A and B as inputs, and Y as output. If B is guaranteed to have 1s, then Y should be 1.

Continue reading → Design a circuit that detects if one input is a delayed version of the other

What are common CDC considerations to transfer a pulse and to transfer multi-bit signals?

CDC considerations to transfer a pulse

Transfer a pulse from slow to fast clock domain, and from fast to slow clock domain, require separate handling.

Generally speaking, passing a signal from slow clock to fast clock is not a problem, since the loss of a pulse is less likely to happen. Based on Nyquist Theorem, if receiving clock frequency is at least 2x of sending clock frequency, then there will be no sampling loss.

Continue reading → What are common CDC considerations to transfer a pulse and to transfer multi-bit signals?

What is MTBF? Why can synchronizers handle CDC?

What is MTBF?

For most applications, it is important to calculate the Mean Time Before Failure / MTBF for any signal crossing a CDC boundary. In the context of MTBF, the failure means the output of the synchronizer still goes metastable. Obviously, a larger MTBF is favored over a smaller one, and the synchronization scheme needs to guarantee sufficient larger MTBF.

MTBF is inversely proportional to input data changing rate as well as receiving clock frequency. The faster of input data rate and receiving clock, the lower of MTBF.

Interviewees often mix the concept of input data changing rate with sending clock frequency, and incorrectly think sending clock frequency does impact MTBF. Faster sending clock does not necessarily imply faster input data changing rate.

It is required to flop the data in sending clock domain before synchronized in receiving clock domain. The output of combo logic often have glitches, i.e., it requires some time to settle. Without data flopping, the input data changing rate is effectively increased in receiving clock domain, decreasing the MTBF of CDC circuit.

Why can synchronizers handle CDC?

The simplest synchronization scheme is back-to-back flop synchronizer. Even though the output of the first stage is metastable, the CDC signal still have one more cycle to settle to a stable logic value. Therefore, synchronizers essentially increase the MTBF.

Conclusion

We recommend interviewees to further read Clifford E. Cummings’ paper “Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog”.

How to specify SGDC / CDC constraints?

Before running Spyglass CDC flow, we need to provide some inputs to Spyglass. One of the most important inputs is SGDC constraints. Usually, in SGDC constraints, designers are required to specify:

  1. Current design, to limit the scope of CDC check
  2. List of source clocks and generated clocks
  3. List of valid abstract port / input constraints. Designers can derive these constraints from SDC such as “set_input_delay
  4. List of valid output constraints. Designers can derive these constraints from SDC such as “set_output_delay
  5. List of valid clock groups constraints. Designers can derive these constraints from SDC such as “set_clock_group”. Unlike STA, CDC flow by default assumes all clocks are asynchronous to each other, and it will attempt perform CDC check against all clock pairs. Designers shall use “set_clock_groups” to specify which clock pair is synchronous, thus CDC check is not required for such clock pair.

Continue reading → How to specify SGDC / CDC constraints?