Metastability happens when a register / FF has a setup or hold time violation. When setup time or hold time violation occurs, the output of that register becomes metastable, i.e., entering a quasi-static state which settles to either low or high.
Design engineer needs to handle properly:
- For synchronous paths, all timing paths should be checked for setup time and hold time constraints. Designers rely on STA to perform a thorough check against all timing paths.
- For asynchronous paths, designers should implement proper synchronization for clock domain crossing / CDC. Proper synchronizations between clock domains make sure metastability does not occur, otherwise chip failure can happen. Designers rely on CDC check to make sure synchronization are properly implemented.