Xilinx Vivado Projects (Verilog HDL)
FPGA Boards
- Basys3
- Nexys4
Vivado Tutorial
Lab 1 – Modeling Concepts
Lab 2 – Numbering Systems
Lab 3 – Multi-Output Circuits
Lab 4 – Tasks, Functions, and Testbench
Lab 5 – Modeling Latches and Flip-Flops
Lab 6 – Modeling Registers and Counters
- Instruction
- Source (Not Needed)
Lab 7 – Behavioral Modeling and Timing Constraints
- Instruction
- Source (Not Needed)
Lab8 – Architectural Wizard and IP Catalog
- Instruction
- Source (Not Needed)
Lab9 – Counters, Timers, and Real-Time Clock
- Instruction
- Source (Not Needed)
Lab10 – Finite State Machines
- Instruction
- Source (Not Needed)
Lab11 – Sequential System Design using ASM Charts
- Instruction
- Source (Not Needed)
Altera Quartus Projects (Verilog HDL and OpenCL)
Developer IDE
eBooks
Tutorials
- Getting Started with the DE-Series Boards
- Quartus Introduction (Pro Edition)
- Quartus Introduction (Standard Edition)
- Quartus Introduction Using Schematic Designs
- Using the Library of Parameterized Modules (LPM)
- Using TimeQuest Timing Analyzer [Source]
- Introduction to Quartus Simulation
- Using ModelSim to Simulate Logic Circuits [Source]
- Introduction to ModelSim’s Graphical Waveform Editor
- Signal Tap II Logic Analyzer
- Debugging of Hardware Designs
Labs
- Lab 1 – Switches, Lights, and Multiplexers [Source]
- Lab 2 – Numbers and Displays
- Lab 3 – Latches, Flip-flops, and Registers
- Lab 4 – Counters
- Lab 5 – Timers and Real-Time Clock
- Lab 6 – Adders, Subtractors, and Multipliers
- Lab 7 – Finite State Machines
- Lab 8 – Memory Blocks
- Lab 9 – A Simple Processor
- Lab 10 – An Enhanced Processor
- Lab 11 – Implementing Algorithms in Hardware
- Lab 12 – Basic Digital Signal Processing [Source]
High-level Synthesis Projects (Vivado HLS)
Lab 1 – Vivado HLS Design Flow
Lab 2 – Improving Performance
Lab 3 – Improving Area and Resource Utilization Lab
Lab 4 – Creating a Processor Sysetem
Instructions
Source
Embedded System Design Projects (Vivado)
Instructions
Source
