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How to reduce static power, dynamic power, and short-circuit dissipation power?

Static Power

Static power is proportional to circuit leakage current and supply voltage Vdd. Thus we have following ways to reduce static power:

  1. Dynamic Vth scaling by adjusting substrate bias
  2. Use multi-Vth devices in design
  3. Use high-Vth device whenever possible
  4. Dynamic supply voltage scaling
  5. Use multi-Vdd in design
  6. Shut off the power in standby mode

Continue reading → How to reduce static power, dynamic power, and short-circuit dissipation power?

What are static power, dynamic power and short-circuit dissipation power?

Static power is the circuit leakage power. Static power exists even if there is no activities. When power is applied to the transistors, transistors would leak current naturally due to physical characteristics of the silicon and manufacturing defects. Examples of static power include transistor drain to source leakage and silicon substrate leakage.

Dynamic power is the power used to charge or discharge transistor intrinsic capacitor. Dynamic power only exists when signals toggle either from low-to-high or high-to-low. For example, clock toggles every cycle, thus clock paths consumes huge amount of dynamic power if there is no clock gating.

Short-circuit dissipation power occurs when both NMOS and PMOS transistors are active for a small period of time, during which current will find a path directly from power rail to ground. Hence, this creates a short-circuit current. In first-order analysis, we assume 0 transistor rise / fall time during transition, and short-circuit dissipation power can be ignored. However, we shall assume finite transistor transition time in more accurate analysis, thus short-circuit dissipation power exists every time signal toggles.

What is metastability?

Metastability happens when a register / FF has a setup or hold time violation. When setup time or hold time violation occurs, the output of that register becomes metastable, i.e., entering a quasi-static state which settles to either low or high.

Design engineer needs to handle properly:

  1. For synchronous paths, all timing paths should be checked for setup time and hold time constraints. Designers rely on STA to perform a thorough check against all timing paths.
  2. For asynchronous paths, designers should implement proper synchronization for clock domain crossing / CDC. Proper synchronizations between clock domains make sure metastability does not occur, otherwise chip failure can happen. Designers rely on CDC check to make sure synchronization are properly implemented

What are setup/hold time constraints and timing violation?

In previous post, we discussed setup time and hold time definitions. We will cover the basics of STA: setup time and hold time constraints.

These constraints dictate the max and min delays of a computational logic between flip-flops. If any of the constraint is not met, we call it as timing violation. Timing violations lead to metastability.

Continue reading → What are setup/hold time constraints and timing violation?

What are setup time and hold time?

When clock start rising, the outputs might start to change after the clock-to-q contamination delay, known as tccq and shall absolutely settle down to the stable value within the clock-to-q propagation delay, tpcq. They represent the shortest and longest delays through the circuit. In order for a circuit to sample its input correctly, the inputs must be stabilized at least some setup time, tsetup, before the rising edge of the clock and shall remain stable for at least hold time, thold.

The definition of setup time and hold time is often asked in hardware interviews. We recommend readers to memorize the definition. In next post, we will cover the setup time and hold time constraints.