2. Micro-architecture Design

2.1. Common Design Blocks

• • Valid-Ready protocol and register slice
    • Valid-Ready protocol and register slice
  • FIFO
    • Synchronous FIFO
      • Decide/Calculate FIFO Depth  
      • Design a non-power-of-2 synchronous FIFO 
      • Design a dual-port SRAM based synchronous FIFO
      • Design a single-port SRAM based synchronous FIFO
    • Asynchronous FIFO
      • Design an async FIFO using flops
      • Design an async FIFO with non-power-of-2 even number of entries
      • Design an async FIFO using SRAMs
  • CDC
    • CDC Considerations
      • What is metastability?
      • What is MTBF? Why can synchronizers handle CDC?
      • What are CDC considerations to transfer a pulse and to transfer multi-bit signals?
    • CDC data transfer techniques
      • How to synchronize a signal/data from slow clock domain to fast clock domain?
      • How to synchronize a signal/data from fast clock domain to slow clock domain?
      • How to synchronize a multi-bits data bus?
  • Arbiters
    • Fixed priority arbiter design
    • Round robin arbiter: the wrong design and the right design
    • Weighted round robin arbiter
  • LRU
    • How to implement true LRU? (I)
    • How to implement true LRU? (II)
    • How to implement pseudo LRU?
  • Reordering
    • How to design a memory controller with in-order read responses?
  • Flow Control and Buffer Sizing
  • Frequency Divider
  • Error Handling and Interrupt
  • Cache Design
  • Adder & Multipliers

2.2. Power and Power Saving Techniques

• • What are static power, dynamic power, and short-circuit dissipation power?
  • How to reduce static power, dynamic power, and short-circuit dissipation power?
  • A review of clock gating cells