2.1. Common Design Blocks
-
- Valid-Ready protocol and register slice
- FIFO
- Synchronous FIFO
- Asynchronous FIFO
- CDC
- CDC Considerations
- CDC data transfer techniques
- Arbiters
- LRU
- Reordering
- Flow Control and Buffer Sizing
- Frequency Divider
- Error Handling and Interrupt
- Cache Design
- Adder & Multipliers