4. Integration and Synthesis

4.1. High Level Synthesis (HLS)

• • What is High Level Synthesis?
  • What are the shortcomings/limitations of High Level Synthesis?

4.2. RTL Synthesis Flow

• • What is ZWL synthesis / sanity synthesis?
  • What is topographical synthesis / production synthesis?
  • What are the basic setups before running synthesis? How to do “set_app_var” and create milkyway library?
  • What is Design Compiler / DC synthesis flow? Can you write a simple DC synthesis script?
  • What are the common DC synthesis optimization techniques?
  • What to check before running synthesis?

4.3. Lint Flow

• • What are the most critical errors in lint?

4.4. CDC Flow

• • How to specify SGDC / CDC constraints?

4.5. RDC Flow

• • What are the differences between sync and async reset?
  • What does RDC check?
  • What are common RDC techniques / schemes?

4.6. LEC Flow

• • What is LEC? Why should we do LEC?
  • What is Conformal LEC flow? How does Conformal LEC perform key point mapping?

4.7. Design Constraints

• • What are design / library objects? How to manipulate these objects?
  • How to set single-clock constraints in Pre-CTS run?
  • How to set interface constraints for single-clock design in Pre-CTS run?
  • How to set multi-synchronous-clock design constraints?
  • How to set generated clock design constraints in Pre-CTS run?
  • How to set mutually exclusive synchronous clock design constraints?
  • How to set asynchronous clock design constraints?

4.8. Low Power Design

• • Why is isolation cell required in power aware design?
  • How many types of isolation cells are there?