5.1. Timing and STA
- What does STA do? What does “synchronous” mean?
- What are setup time and hold time?
- What are the setup/hold time constraints and timing violations?
- What is the benefit of using half-cycle-path?
- What is metastability?
- What are the sources for clock uncertainty?
- What are additional timing constraints that STA should check?
- How does STA verify asynchronous FIFO functionality?
- How does STA check latch based design?
- What are design / library objects? How to manipulate these objects?
- How to set single-clock constraints in Post-CTS run?
- How to set interface constraints for single-clock design in Post-CTS run?
- How to set multi-synchronous-clock design constraints?
- How to set generated clock design constraints in Post-CTS run?
- How to set mutually exclusive synchronous clock design constraints?
- How to set asynchronous clock design constraints?