4.1. High Level Synthesis (HLS)
4.2. RTL Synthesis Flow
- What is ZWL synthesis / sanity synthesis?
- What is topographical synthesis / production synthesis?
- What are the basic setups before running synthesis? How to do “set_app_var” and create milkyway library?
- What is Design Compiler / DC synthesis flow? Can you write a simple DC synthesis script?
- What are the common DC synthesis optimization techniques?
- What to check before running synthesis?
4.3. Lint Flow
4.4. CDC Flow
4.5. RDC Flow
4.6. LEC Flow
4.7. Design Constraints
- What are design / library objects? How to manipulate these objects?
- How to set single-clock constraints in Pre-CTS run?
- How to set interface constraints for single-clock design in Pre-CTS run?
- How to set multi-synchronous-clock design constraints?
- How to set generated clock design constraints in Pre-CTS run?
- How to set mutually exclusive synchronous clock design constraints?
- How to set asynchronous clock design constraints?