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5 Comments

    1. Do you mean parameterized module? Parameterized port list is used for making the parameterized modules. Instead of designing the module with fixed port length.

      For example, to make a 32 bits multiplexer,
      // we could write in fixed length
      module mux2
      (input [31:0] din1, din2,
      input sel,
      output [31:0] dout);

      assign dout = sel ? din1 : din2;
      endmodule

      // or we could make the module size parameterizable so that people could assign in different “WIDTH”
      module mux2 #(parameter WIDTH=32)
      (input [WIDTH-1:0] din1, din2,
      input sel,
      output [WIDTH-1:0] dout);

      assign dout = sel ? din1 : din2;
      endmodule

    1. For loop in C is used for iterating/executing certain computations, while for loop in Verilog HDL is used for generating certain hardware blocks multiple times and connect them together. Thus, to use a for loop generator in RTL coding you will need to carefully define the ports and relationships of the connections.

  1. Can anyone explain me the concept of sectioning in cache? (I referred on Internet it basically says sectoring is different kind of write strategy in caches in which the block is fetched only if the entire blocks are not written frequently)

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