Verilog Coding
Basics
- What’s the difference between blocking and non-blocking assignments?
- How to detect and resolve x-related issues in RTL?
- What is the difference among casex, casez and case-inside?
- What’s the difference between Mealy and Moore Machines?
- What are universal gates?
Diagram
- Draw the logical block diagram which the following Verilog code is synthesized to
- Design a simple ALU and draw its logical block diagram
Multiplexer
Arithmetic Logic Units
- Design a parameterized fix-point multiplier (signed)
- Design a parameterized fix-point adder (signed)
- Design a parameterized floating-point multiplier (signed)
- How to implement w = 3/2 x + 1/4 y + z?
- How to implement multiplication by 5 for BCD code?
Sequence Detector
- Design a circuit which detects signal toggling
- Design a circuit that detects sequence 010101 (Draw FSM & HDL)
- Design a circuit that detects sequence 1(01)*1
- Design a circuit that detects if one input is a delayed version of the other
- Design a circuit that detects 3b palindrome
- Determine whether an infinite sequence is a multiple of 5
- Design a programmable sequence detector
Sequence Generator
Memory Design
- Design a single-port synchronous RAM (Read first)
- Design a single-port synchronous RAM (Write first)
- Design single and dual-port asynchronous read RAM
- Design a synchronous ROMs using BlockRAM
- Design a dual-port RAM with two clocks from different clock domains
CDC Data Transfer
- Design a 4-phase REQ-ACK CDC handshake sender and receiver module
- Design a 2-phase REQ-ACK CDC handshake sender and receiver module
