Until now, we focus on the timing of one-cycle-path or full-cycle-path. Sometimes, there may exist half-cycle-path in design. One example will be the launch flop is negedge triggered, while the capture flop is still posedge triggered.
We discussed the clock skew and how it affects STA in previous post. Equivalently, half-cycle-path can be modeled as one-cycle-path with clock skew δ = +T/2. It is obvious that hold time closure is easier while setup time closure is harder for half-cycle-path.
You may wonder what is the benefit of using half-cycle-path in the design.
Assuming transmitter wants to transfer 32B data to receiver, and the data is source synchronized, i.e., transmitter will forward the clock along with data to receiver. Such path will have large positive clock skew δ, thus setup time closure will be straightforward. However, hold time check may have violations.
To fix hold time in such case, there are 2 possible solutions:
- Add buffers in datapath, i.e., trading the setup time for hold time
- Make launch flop negedge triggered while capture flop posedge triggered, i.e., using half-cycle-path
Apparently, the 2nd solution is cleaner.
In next post, we will discuss the sources of clock certainty.