Interviewees who are not familiar with BCD code, we recommend to read this link first.

Assume the BCD code value is within the range between 0 and 9. Thus we can use the table below to show the inputs and outputs of the multiplier.

Decimal input

BCD coded input Decimal output BCD coded output

0

0000 0000 0 0000 0000
1 0000 0001 5

0000 0101

2

0000 0010 10 0001 0000

3

0000 0011 15

0001 0101

4 0000 0100 20

0010 0000

5

0000 0101 25 0010 0101
6 0000 0110 30

0011 0000

7

0000 0111 35

0011 0101

8

0000 1000 40

0100 0000

9 0000 1001 45

0100 0101

Apparently, for even number decimal input, BCD coded output LSB 4 bits will be 0000; for odd number decimal input, BCD coded output LSB 4 bits will be 0101.

BCD coded output MSB 4 bits will be shifted version of BCD coded input [3:1].

Thus the Verilog implementation is shown below.

 

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