by Given the ALU pseudo code below, write the Verilog code and draw its logical block diagram using only 1 full adder, bitwise OR/AND, and as fewer MUXes as possible.
|
1 2 3 4 5 6 |
if (sel == 0) result = A + B; else if (sel == 1) result = A - B; else if (sel == 2) result = A & B; else if (sel == 3) result = A | B; else if (sel == 4) result = PC + offset; else result = 0 |
Verilog implementation should be straightforward:
|
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 |
Module ALU ( input [15:0] A, input [15:0] B, input [15:0] PC, input [15:0] offset, input [2:0] sel, output logic [16:0] result) always_comb begin result = ‘0; case(sel) 3’b000: result = A + B; 3’b001: result = A - B; 3’b010: result[15:0] = A & B; 3’b011: result[15:0] = A | B; 3’b100: result = PC + offset; endcase end endmodule: ALU |
The logical block diagram below shows one possible physical implementation. Note, the solution below uses 5 MUXes in total.
Leave a Reply