CPU pipelining is a common technique to increase throughput and instruction level parallelism. Can we arbitrarily increase the CPU pipeline depth? Short answer is NO.
This is an open question. We recommend interviewees to answer this question from the following aspects:
- Pipeline needs to be balanced between each stage. Otherwise there will be bottleneck. Usually the deeper the pipeline, the harder the design can be pipelined.
- Deeper pipelining requires more hardware resources, for example, more pipeline stage registers, and more ROB entries to implement precise interrupts as well as hardware-based speculation
- CPU pipeline needs to deal with structural / data / control hazards. The deeper the pipeline, the more complex the control logic is
- Control hazards may force pipeline flushing, thus theoretical peak performance is seldom reached
- Data hazards may block subsequent operations, thus certain parallelisms cannot be exploited
- Deep pipeline introduces issues in physical implementations, for example, clock tree balancing and clock skews
- Deep pipeline adds up instruction latency
- The logic behind this approach is, if the pipeline is deeper, we may further increase the clock frequency and pipeline throughput. However, there is an upper bound of the clock frequency that certain technology node can offer. Thus there is no point increasing pipeline depth arbitrarily