Synchronous reset has the following characteristics:

  1. It will not work if clock path has failures
  2. It tends to immune to glitches, since sync reset requires clock toggling
  3. It makes STA simpler and the whole design synchronous, since sync reset has no difference from regular data path
  4. Sync reset implementation will add a MUX at the input of each flop

Asynchronous reset has the following characteristics:

  1. It does not require clock toggling to reset the logic
  2. Unintended glitches on async reset line will introduce catastrophic effect
  3. Async reset introduces async timing path in the design, since the reset can take effect at any time, leading to possible metastability issues. Usually async reset is released synchronously by using reset synchronizers, and STA needs to check reset removal time and recovery time
  4. Async reset is implemented inside the flop, in transistor level. Please see the diagram below extracted from this link.

We recommend interviewees to read this paper “Asynchronous & Synchronous Reset Design Techniques – Part Deux” for more details.

The existence of async reset in the design requires RDC check, which we will discuss in the next post.

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