Assuming 1b input A is generated by a random sequence, 1b input B is a delayed version of A. The delay value varies, and can be [1, 10] (inclusive).

Design a circuit, that takes A and B as inputs, and Y as output. If B is guaranteed to have 1s, then Y should be 1.

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module dly_seq_dec ( input clk, input rst_n, input A, input B, output logic Y ) logic [3:0] cnt; // represent delay value up to 10 always_ff@(posedge clk or negedge rst_n) if (~rst_n) cnt <= ‘0; else if (A | B) cnt <= cnt + A - B; assign Y = (cnt != 4’d0); endmodule: dly_seq_dec |

Obviously, “cnt” should be [0, 10]. If “cnt” > 10, then B is delayed for more than 10 cycles, and this is considered to be a spec violation. Designers should consider to have an SVA for this case.

If “cnt” < 0, then B is not a delayed version of A. This can happen when B sees a 1 but A never sees a 1. Designers should consider to write an SVA to detect the spec violation. In addition, “cnt” should be extended from 4b to 5b, and the MSB of “cnt” is for the sign extension.

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