Assuming sender block uses clk1, while receiving block uses clk2. Sender block and receiving block use 2-phase REQ-ACK protocol for clock domain crossing.

Also assume the sender block interacts with its upstream logic using valid-ready protocol, and the receiving block interacts with its downstream logic using valid-ready protocol.

We mentioned in previous post that, 2-phase REQ-ACK protocol is faster than 4-phase, but it is also less robust compared to 4-phase.

In 2-phase REQ-ACK protocol, if only transmitting side goes to reset, REQ may have an unwanted toggle from 1 to 0. From receiving side’s perspective, this is considered as a valid data transfer, but data captured by receiving side may be unknown. This can cause metastability issue in receiving side.

 

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