In today’s SoC design, designers use clock gating cells everywhere to save dynamic power by reducing unnecessary clock activities inside the gated module. In addition, the use of ICGs can save area. Imagine a 512b data bus can be enabled or disabled using a single ICG, instead of using 512 muxes.

There are mainly 4 types of clock gating cells available:

Negative-Latch-AND-Gate Based ICG
OR-Gate Based ICG
Positive-Latch-OR-Gate Based ICG
AND-Gate Based ICG

Negative-Latch-AND-Gate Based ICG

This is most commonly used ICG in posedge triggered design: the neg-latched clock enable signal will qualify with the clock directly.

As shown in the diagram below, the gated clock stays at LOW when clock is off.

If the downstream logic is a neg-latch, then we should not use this ICG. Otherwise the neg-latch is transparent when clock is gated.

In this ICG, we cannot replace the AND gate with an OR gate. Or we will see glitches on GCLK when neg-latch output toggles from 0 to 1, marked in the dotted timing window in the diagram below.

OR-Gate Based ICG

An alternative ICG used in posedge triggered design is OR-gate based. See the diagram below:

When clock is off, gated clock stays at HIGH. Thus this OR-gate based ICG can be used to clock neg-latch in posedge triggered design.

Positive-Latch-OR-Gate Based ICG

This is most commonly used ICG in negedge triggered design: the pos-latched clock enable signal will be inverted first, then ORed with the clock directly.

As shown in the diagram below, the gated clock stays at HIGH when clock is off.

If the downstream logic is a pos-latch, then we should not use this ICG. Otherwise the pos-latch is transparent when clock is gated.

In this ICG, we cannot replace the OR gate with an AND gate. Otherwise we will see glitches on GCLK when pos-latch output toggles from 1 to 0, marked in the dotted timing window in the diagram below.

AND-Gate Based ICG

An alternative ICG used in negedge triggered design is AND-gate based. See the diagram below:

When clock is off, gated clock stays at LOW. Thus this AND-gate based ICG can be used to clock pos-latch in negedge triggered design.

Conclusion

Among these 4 types of ICGs, simple OR-gate / AND-gate based ICGs are less common. One interesting characteristic of simple OR-gate / AND-gate based ICGs is, the polarity of the gated clock when clock is off is inverted compared to their latch based counterparts. Therefore, they sometimes are interview question candidates to test the understanding of ICG.

We use the table below to summarize all 4 types of ICGs:

Negative-Latch-AND-Gate Based ICG OR-Gate Based ICG Positive-Latch-OR-Gate Based ICG AND-Gate Based ICG
Posedge / negedge triggered design posedge triggered posedge triggered negedge triggered negedge triggered
GCLK value when clock is off LOW HIGH HIGH LOW
GCLK used to clock LOW / HIGH transparent latches HIGH transparent latches LOW transparent latches LOW transparent latches HIGH transparent latches

 

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