This code infers a 3-to-1 1-bit MUX with a 1-bit latch. The latch will be inferred as s=2’b11 is not specified in the code.

Draw the logical block diagram which the following Verilog code is synthesized to

1 Comment

  1. When s=2’b11, the output o should retains its previous value (as it was not specified in the code). So the latch should be opaque. So the latch should be transparent in all the other cases (00, 01 and 10). Hence, this should not be an AND gate controlling the latch.

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